ASIC prototyping debug solution eliminating recompiles

TEKTRONIX Certus 2.0 ASIC prototyping debug suite of software and RTL-based embedded instruments changes the ASIC prototyping flow by enabling full RTL-level visibility and making FPGA internal visibility a feature of the prototyping platform. This simulation-level visibility allows engineers to diagnose multiple defects in a day versus a week or more with existing tools. Product allows designers to automatically instrument all the signals likely to be needed in each of the FPGAs in a multi-FPGA ASIC prototype with a small FPGA LUT impact.

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