32-BIT RISC CORE: XAP3 ASIC

The XAP3 core is available in Verilog RTL and can be fabricated in under 50,000 gates in a variety of ASIC and FPGA technologies. XAP3?s instruction set has been optimized to exploit the code-efficient features of state-of-the-art C compiler technology, substantially reducing memory requirements and power consumption. It supports position independent code and privileged modes, giving IC developers and their users a platform to create more versatile, robust, field-upgradeable products.
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