Synopsys ASIP Designer Workshop
October 17, 2019
Registration is now open. On October 17, join CMC Microsystems and Synopsys, Inc. at Polytechnique Montréal for a 1/2-day workshop demonstrating the capabilities and benefits of the Synopsys ASIP Designer environment for applications such as AI and 5G. In this workshop featuring live demonstrations and both industrial and academic use cases, attendees will explore how to develop custom processors and hardware accelerators for ASIC and FPGA demonstration using industrial-grade tools.
For the full program and registration, go to: https://www.cmc.ca/asip-designer-workshop/
About ASIP Designer
Synopsys’ ASIP Designer is a tool suite that brings ASIP design within easy reach of every SoC team. Key capabilities include rapid exploration of architectural choices, generation of an efficient C/C++-compiler based software development kit that automatically adapts to every architectural change and automatic generation of power and area-optimized synthesizable RTL.
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