Accelerate adaptive SoC and FPGA development

September 13, 2023

Accelerate adaptive SoC and FPGA development with Vitis Model Composer and Vivado Design Suite

Presented by AMD

Time: 8AM PDT/11AM EDT/5PM CEST

Vitis™ Model Composer provides an efficient environment for algorithm development and model-based design. Vitis Model Composer also offers various techniques to boost the development process and streamline the integration of complex IPs into the designs.

In this webinar, we will cover:

• Developing an IP with Vitis Model Composer and integrating it into the Vivado™ integrated design environment
• Importing an externally developed IP into Vitis Model Composer using the HDL Black Box block

Join us to gain valuable insights that will empower you to maximize the potential of adaptive SoC and FPGA designs from AMD, create robust and efficient hardware designs, and accelerate your development process.

Featured Speaker

Rob Graessle, Staff Product Applications Engineer, AMD