Plugfest Advances Adoption of MIPI I3C Designs
EP&T MagazineElectronics Regulations & Standards
San Jose event assembles MIPI I3C/I3C Basic and Debug for I3C implementers for interoperability testing across multi-vendor devices
The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, announced the successful completion of a MIPI I3C and Debug for I3C interoperability testing event in San Jose, Calif.
The June 26-27 plugfest, which coincided with MIPI’s 63rd member meeting, engaged 26 MIPI I3C/I3C Basic and Debug for I3C implementers from 10 companies in a range of interoperability testing (from initial to advanced) for their designs. An increase in participation and a broader array of devices from previous interoperability testing events signifies the growing importance and breadth of applications for the I3C specification.
Participants tested for interoperability between multi-vendor controller and target devices in a confidential environment with a mix of electronics manufacturers. Acute Technology Inc., Arasan Chip Systems Inc., Binho LLC, Cadence Design Systems, Inc., Intel Corporation, Introspect Technology, Microchip Technology Inc., Prodigy Technovations Pvt. Ltd., STMicroelectronics, and Tektronix Inc., were among the companies involved in the plugfest.
- MIPI I3C is a scalable, two-wire utility and control bus interface for connecting peripherals to an application processor, giving developers unprecedented opportunities to craft innovative designs for an array of products—smartphones, personal computers, wearables, IoT devices, systems in automobiles and other devices. Designed as the successor to I2C, I3C incorporates key attributes of the traditional I2C and SPI interfaces to provide a high-performance, very-low-power solution with backward compatibility and a robust, flexible upgrade path. MIPI I3C is available to MIPI members.
- The publicly available, royalty-free MIPI I3C Basic is a subset of I3C that bundles the most commonly needed I3C features for developers and other standards organizations. MIPI I3C Basic has been adopted into JEDEC’s Sideband Bus and DDR5 standards, and it has been adopted by ETSI Technical Committee Secure Element Technologies (TC SET) as a physical and logical link layer for the ETSI Smart Secure Platform (SSP).
- MIPI Debug for I3C is a bare-metal interface that allows system designers to debug and test application processors, power management integrated circuits, modems and other power-managed components across a system via the I3C interface.
“Plugfests are pivotal gatherings for the evolution of innovation and an opportunity to work together to strengthen the ecosystem,” said Sanjiv Desai, chair of MIPI Alliance. “The MIPI I3C and Debug for I3C Plugfest exemplified the power of collaboration to foster seamless integration and efficiency across a breadth of applications, reinforcing the immense potential of the I3C specification.”