Electronic Products & Technology

Sidense and Intellitech collaborate on electronic chip IDs

Stephen Law   

Electronics Semiconductors Wireless Engineering Supply Chain electronic chip

Firms also combine efforts on anti-counterfeiting and semiconductor security for secure supply chain enablement

Sidense Corp., an Ottawa-based developer of non-volatile memory (NVM) IP cores, and Intellitech, a leader in IEEE 1149.x based standard solutions, have collaborated on a solution that enables an IC designer to easily implement a per-die IEEE 1149.1-2013 Electronic Chip ID with robust anti-tamper and anti-counterfeit security features. The solution forms the basis of secure supply chain enablement by authenticating that the IC is from the source it purports to be from and has passed tests for the speed and temperature grade with which it is marked.  

IEEE 1149.1-2013/JTAG has standardized the general format for ECIDs (Electronic Chip Identification) with a set of description languages for programming and reading it. A basic ECID records the die position on the wafer with a unique ID that enables tracking of the die from wafer to field. This tracking is essential for correlation of failures found in SLT (System Level Test) back to the fabrication process to create improvements in wafer lithography and wafer test. The standard allows extending the ECID to include storage fields for die authentication, anti-cloning and per-die security. ECID also provides the basic foundation, through security keys, for device authentication, a fundamental requirement for secure boot and feature enablement.

Suited for ECID, security key storage and other security related applications

The Sidense 1T-NVM is ideally suited for ECID, security key storage and other security related applications. 1T-NVM is very small with no physically detectable logic ‘state’ (unlike FLASH) that would allow security keys be read or altered. The initial vehicle for this collaboration is the Sidense SHF solution. The SHF comprises a Memory Array, containing the patented 1T-Fuse™ OTP bit cells, an Integrated Power Supply (IPS) and controller. The controller integrates a BOOT function for OTP and IPS power-up, a program and read verify function and a built-in self-test (BIST) capable of defect repairs.


“We are extremely pleased with our ongoing collaboration with Intellitech,” said Andrew Faulkner, Senior Director Product Management, Sidense Corp. “The outcome of this collaboration delivers a turnkey, standards-based solution for tracking die and for anti-cloning protection throughout the IC supply chain.”

The Intellitech NVM Silicon Instrument is Verilog IP that interfaces to the Sidense SHF controller. The instrument uses the IEEE 1149.1-2013 languages to describe recording fields for JEDEC vendor ID, fab, wafer, unique die ID, die X-Y position, speed and temperature grade along with the pass/fail status of the die. A recording field for an optional SHA256 hash of this data is provided as a maximum anti-tamper countermeasure. While the design of the NVM Silicon Instrument and Sidense memory prevents tampering, the SHA256 hash value guarantees that none of the identification data bits have been altered. The Silicon Instrument provides read/write capability to the SHF array through a flexible and programmable firewall, allowing the designer to specify memory locations to be programmed during wafer-probe test but then locked from further reading via JTAG. Similarly, other locations used for the ECID can be programmed and then locked from further programming but are fully readable via JTAG in the field.

“Sidense was quick to recognize that their customers can get to working silicon faster with having pre-engineered standards-based ecosystems built-around their secure SHF 1T-NVM,” said CJ Clark, CEO of Intellitech Corporation.

The solution is completed using Intellitech’s NEBULA software development environment that addresses NVM use from design to fab and field. The designer can write, read, and lock the Sidense 1T-NVM with the IEEE 1149.1-2013 Procedural Description Language (PDL) scripts via the NEBULA software. This can be done pre-silicon via the NEBULA plug-ins that drive verification environments provided by the three major EDA players. A freely available “ECID reader” version of the software is available from Intellitech’s website for authentication of the die by the public.




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