Demand for AI optimized chipsets to spur hybrid bonding
By Dr. Seung Kang, VP of semiconductor strategy, Adeia
ElectronicsRequirements for technology spreads across the semiconductor industry
The rapid rise of new artificial intelligence (AI) applications – boosted recently by broad interest in generative AI (GenAI) – is having a dramatic impact on the semiconductor industry. It is accelerating demand for compute capacity that will outpace the capabilities of current chipset technologies underpinning today’s high-performance infrastructures, platforms and devices, according to Dr. Seung Kang, vice president of strategy at Adeia, a leader in the semiconductor intellectual property arena.
Rising interest in AI across nearly every vertical segment of the global digital economy is expected to drive a surge in demand for hybrid bonding technology across the semiconductor industry.
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According to analysts at Gartner, semiconductors designed to execute AI workloads will represent a $53.4 billion revenue opportunity for the semiconductor industry in 2023, an increase of 20.9% from 2022. AI-centric semiconductor revenue will continue to experience double-digit growth over the next few years, increasing 25.6% in 2024 to $67.1 billion and reaching $119.4 billion by 2027.
AI workloads are computationally intensive
“AI is dramatically impacting the industry because it is accelerating the need for increasingly powerful and energy-efficient computing systems, surpassing the capabilities of incumbent semiconductor platforms. Let me elaborate,” said Kang. “AI workloads are computationally intensive, demanding semiconductor systems that are customized for massive parallel computing.”
Currently, the key drivers of such systems are a graphics processing unit (GPU) and high-bandwidth memory (HBM) which are coherently integrated with high-speed interconnects. To meet state-of-the-art AI system requirements, unprecedented performance benchmarks are needed. This is especially true when dealing with large language models. However, both processors and memory components face fundamental semiconductor scaling challenges.
“GPUs and AI-customized neural processors rely on cutting-edge logic nodes that offer a smaller footprint, lower power consumption and faster speed. As the demand for computing performance continues to grow, realizing such processors on a monolithic chip — even at the most advanced node — becomes increasingly challenging. In such cases, the desired approach is to disaggregate and reassemble chips in new form factors without significant trade-offs,” Kang explained.
There is a growing consensus in the industry that hybrid bonding technology will become widely adopted both for processors and for HBMs. Compared with other methods, hybrid bonding offers inherent advantages in high-density IO (input-output), reduced parasitic delay, shorter height and improved thermal performance.
Hybrid bonding explained
Hybrid bonding is a method to interconnect semiconductor wafers or dies by combining metal-to-metal and dielectric-to-dielectric bonding. It is commonly associated with Direct Bond Interconnect (DBI?, DBI? Ultra). Hybrid bonding is a direct bonding technology that interconnects wafer-to-wafer, die-to-wafer and die-to-die at an ultra-fine pitch without the need for solder or other adhesives.
“Hybrid bonding finds applications today in 3D heterogeneous integration scenarios where different types of chips – designed for different functions or from different suppliers – are seamlessly integrated and made interoperable. The evolving requirements of AI systems are expected to surpass the capabilities of conventional semiconductor system architectures. This trend is driving the industry towards adopting disaggregated multi-chip configurations. Hybrid bonding is well-positioned as a compelling technology to underpin and facilitate these innovative semiconductor architectures,” says Kang.
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Dr. Seung Kang is vice-president of semiconductor strategy at Adeia, and currently leads strategic semiconductor programs that include technology, design and system co-optimization. Adeia licenses its hybrid bonding portfolio to various semiconductor markets, including memory, logic, RF and image sensor.
