Electronic Products & Technology

PCIe 6.0 interface subsystem serves high-performance data centre, AI SoCs

Stephen Law   

Semiconductors AI PCIe SoCs

RAMBUS PCI Express (PCIe) 6.0 Interface Subsystem comprised of PHY and controller IP supports the latest version of the Compute Express Link (CXL) specification, version 3.0. Subsystem supports the performance requirements of next-generation data centres with best-in-class latency, power, area and security. Interface subsystem delivers data rates of up to 64 Gigatransfers per second (GT/s) and has been fully optimized to meet the needs of advanced heterogenous computing architectures. Within the subsystem, the PCIe controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. On the PHY side, full support for CXL 3.0 is available to enable chip-level solutions for cache-coherent memory sharing, expansion and pooling. Product offers complete IP solution optimized for latency, power, and area, while delivering cutting-edge security to protect valuable data assets.

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