FPGAs boost I/O density, lower power signal bridging
LATTICE SEMICONDUCTOR MachXO2ZE FPGA family with wafer level chip-scale packaging (WLCSP) and increased I/O density comes in package sizes as small as 2.5 x 2.5mm, standby power levels as low as 22μW, and up to 63 general-purpose I/Os (GPIO). Devices are a suitable hardware platform for signal bridging and/or interface applications in smart consumer and industrial IoT devices operating at the network Edge. Devices combine a low-power, small form factor FPGA fabric with Embedded Block RAM (EBR), Distributed RAM, and User Flash Memory (UFM) blocks developers can use to implement a variety of functions in high-volume Edge devices. Other capabilities such as robust I/O support (1.2 to 3.3V), low-voltage differential signaling (LVDS), and integrated phase lock loops (PLLs) further broaden the scope of applications these devices can support.