August 24, 2023

Guidelines for System-Level JTAG Design

Time; 11:30 AM – 12:30 PM EDT

Sponsored by Asset

JTAG is known as a foundational technology for boundary scan test, firmware debug, device programming and platform validation of individual chips and printed circuit boards. But, it is lesser known that it can also be used in a system-level framework; providing services in complex structures ranging from multi-chip modules to entire chassis-based board-to-board architectures.

In this webinar, ASSET’s Michael Johnson will do a deep dive into the hardware design rules behind the use of JTAG, boundary scan, and related applications at a system level.