Electronic Products & Technology

The PHY driving innovation in mobile performance

By Chris Loberg, senior technical marketing manager, Tektronix   

Test & Measurement Wireless

About 3-billion MIPI-powered ICs were shipped in 2012, but of those only 100-million were based on the high-performance, low-power M-PHY specification. That is certain to change in the coming years as M-PHY will be used in the development of high-end mobile devices to deliver increased performance, effective power management schemes, robustness against RF interferences and low RF emission.

For designers accustomed to working with such high-speed serial standards as USB and PCI Express, M-PHY’s changeable gears, terminations and amplitudes will introduce a new set of testing challenges. For mobile designers who have been working with slower speeds, the higher speeds available in M-PHY will create new signal integrity challenge to manage timing/jitter and noise. Receiver stress testing will also be a requirement for the high speed gears (HS2, HS3).

The MIPI M-PHY specification realizes the MIPI Alliance’s vision of a single low-power, mobile PHY, powerful enough to address existing and future mobile devices requirements. It is the mobile PHY of the future for smartphones, tablets and will likely power next generation devices that merge the power of a PC with the responsiveness and long battery life of mobile devices.

The MIPI first PHY standard, D-PHY, was introduced in 2005 and can be found in most mobile devices today. D-PHY is commonly used to connect an applications processor to a camera using the MIPI Camera Serial Interface (CSI) and to connect the applications processor to the mobile device’s display using the MIPI Display Serial Interface (DSI). D-PHY’s reach has not extended beyond the camera and display due to inherent architectural limitations restricting the transmission rate to 1.5 Gbps. This was not seen as a limitation several years ago, but is too slow to handle the data traffic in today’s smartphones and tablets.


The M-PHY specification was fresh start designed for the long haul. This effort resulted in a serial, low pin count, embedded clock PHY that offers multiple transmission and power-saving modes. The M-PHY supports data rates from 10kbps up to 5.8Gbps, enough bandwidth to support the various data interfaces within a mobile device. Interfaces employing M-PHY now include several MIPI standards (CSI-3, DSI-2, LLI, UniPro, and DigRF), the USB SSIC standard, the Universal Flash Storage (UFS) standard, and more recently the M-PCIe standard. The interfaces are organized in a layered stack as shown in Figure 1.

M-PHY transmitter testing

M-PHY transmitter testing involves approximately 1,000 tests across different combinations of gears, sub-gears, amplitudes, and termination for each lane under test. Set-up and reporting requirements are demanding as well. Due to the faster signaling frequency, a number of performance parameters need to be measured for M-PHY devices including slew rate, transition time, pulse width, unit interval, differential DC and common mode voltage, minimum eye opening, power spectral density (PSD) and jitter (long term and short term).

In M-PHY HS measurements, signal validation on the following parameters are checked and validated on the acquired signal:

* Data Rate – The unit interval of an M-PHY burst data signal needs to be computed since data rate variations could be within 2,000 ppm for any HS gear.

* MARKER0 – This parameter (considering both positive and negative disparity) is searched in the acquired waveform. If MARKER0 is present, then the signal validation is passed for this parameter.

M-PHY data transmissions can happen in burst or continuous mode. In burst mode data will have different states including PREPARE, SYNC, MK0, PAYLOAD and STALL. M-PHY has a number of electrical parameters that need to be measured at specific states of the burst. For example, PREPARE length uses PREPARE state, differential DC positive and negative uses PREPARE and STALL respectively. EYE, jitter, transition time and unit interval use MK0, PAYLOAD and MK2 only. From a test perspective, this means the engineer has to identify different states in a burst waveform, place markers or cursors and then measure the required electrical parameter.

M-PHY burst has SYNC and PAYLOAD which are 8b10b encoded; meaning there are no symbols which have more than five continuous ones or zeros (maximum allowed run length of 5 bits). This behavior is used to identify PREPARE and STALL. The remaining part of the waveform (SYNC, MK0, PAYLOAD and MK2) are converted into bits, the location of MK0 (considering both positive and negative disparity) and end of burst are identified and measurements are performed on cursor gated regions.

Transmitter test solutions

To make M-PHY testing less onerous, test and measurement vendors offer automation software that reduces the overall test complexity and reduces the time required to test devices. While not all tests are covered, vendors typically support anywhere from 75 to 95 percent of the most important tests. Multi-lane setups are often also supported, which mean that four lanes of an M-PHY transmitter can be connected simultaneously to four channels on an oscilloscope to help shorten run times. The software also generates a single printable report as shown in Figure 2 for all the different test combinations.

Receiver testing for M-PHY

Receiver testing has many waveform generation needs including non-return to zero (NRZ) signaling, pulse width modulation (PWM) signaling, 8b/10b encoding, reference clock, differential signal generation with common mode DC, and addition of jitter impairments such as ISI, Pj and Rj.

Loopback mode is the most common mechanism for receiver testing, primarily for bit error rate (BER) testing. In M-PHY loopback testing, the receiver routes and re-transmits a recovered M-PHY signal through the transmitter without decoding 8b/10b symbols. Loopback mode requires that both the transmitter and receiver use the same mode and gear. An oscilloscope-based error detector or BERT can perform this testing.

Similar to the transmitter side, software that automates Rx test set and execution can reduce complexity and save time. In addition to an oscilloscope, Rx testing also requires an arbitrary waveform generator. A typical configuration is shown in Figure 3. The software typically support error count testing and provides options to modify the test setup according to device configurations such as the high-speed gear, test time or loopback duration.

Before the receiver test can start, the device under test must be put in loopback mode. Once loopback is set on the DUT, the AWG sends a burst mode signal with recommended patterns for all measurements. The software allows the user to configure the loopback settings initially, and retain them for subsequent test executions by sending the signal continuously during the transition from one test to another. By working together, the AWG and the oscilloscope error detector can complete each measurement in about three minutes.

M-PHY protocol testing

Designers working on M-PHY hardware and firmware designs need to monitor and debug protocol interfaces such as LLI, UniPro and SSIC to ensure reliable operation of the M-PHY system. High speed serial designers prefer familiar instruments such as mixed signal oscilloscopes for both electrical and protocol testing. Oscilloscopes provide extensive details about the electrical characteristics of the signal and with the decode software can provide insight into packet contents at different protocol layers. Decode capability is necessary because trying to manually interpret the protocol layer information using oscilloscope data is time consuming and prone to human errors, particularly for protocol applications as versatile as M-PHY.

Bright future

As PCs become lighter and thinner and tablets and smartphones become more functional, it’s easy to see the emergence of a new class of device that combines all the power of a workstation-class PC with the always on/always connected convenience o
f mobile device. The emergence of M-PHY along with the adaption of popular PC I/O standards to M-PHY will allow component and device manufacturers to reduce product development and validation time by taking advantage of a proven low-power PHY layer. As with any high-speed serial technology verification, compliance testing and debug will be critical to successfully bringing M-PHY based technologies to market.


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