Simple analog ASIC solves difficult thermal analysis problems
EP&T MagazineElectronics Semiconductors Thermal management
In a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. These chips are being built on smaller lithographies, running at higher speeds, dissipating more power and to make things worse, they are being encapsulated in ever decreasing package sizes. What could possibly go wrong?
Plenty! Higher device performance comes at a price; higher temperatures. And with higher temperatures comes lower reliability if thermal considerations aren’t carefully controlled. Semiconductor manufacturers have long been aware of the problems associated with heat. Most have application notes and white papers plastered across their web sites espousing the benefits of careful calculation of power management using their values of 0JA and 0JC (Junction-to-Ambient and Junction-to-Case thermal resistance, respectively) often with sidebars suggesting various heat sinks to use in marginal situations. This puts the burden of solving temperature related problems on the backs of the user.
Recent technology advances and the proliferation of the use of Thermal Test Chips like those developed by JVD Inc. for Thermal Engineering Associates of Santa Clara CA, is allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production.
Thermally engineer your own ICs
Today, almost anyone can design a thermally engineered IC. Whether you’re a designer at a commercial semiconductor company or you’re crafting your own ASIC, the tools are readily available to physically simulate the thermal effects of your design, well in advance of spending any money to produce your first silicon prototypes. Thermal Test Chips (TTCs) allow system designers to fully model, measure and modify their designs before committing to costly silicon.
TTCs are special silicon die (yes, they are Analog ASICs) that are used to model and measure the thermal performance of your chip design in situ before you commit those tooling dollars for masks and wafers.
Modeling allows you to create multiple individual heat sources on the TTC die, identical to the heat sources that will occur on your final IC. Temperature sensors, strategically located throughout the TTC give you precise measurement of the temperature of the die at multiple locations simultaneously. The heat sources can be modulated to replicate various portions of your IC being power on, off or in an intermediate mode. By tracking the absolute or changes in temperature at any point on the TTC, you can determine if one or more heat sources combine to exceed safe operating temperatures of the intended IC design. If temperatures are problematic, you can go back to your IC design and modify the chip’s layout to isolate the heat sources and alleviate the potential problem.
How it’s designed
TTCs are produced like any other Analog ASIC. In this example, the individual Unit Cell is 2.5mm x 2.5mm and each cell contains two heat sources (metal film resistors) and four strategically located temperature.
***See Figure 1a, 1b
It is rare that a thermal analysis would need to be performed on a die as small as 2.5mm x 2.5mm. For this reason, all of the cells on the wafer are interconnected, forming a wafer scale product. This is important because thermal modeling and measurement must be done with a die that closely approximated the size (mass) of the IC being simulated. The wafer scale product can then be sawed into any of hundreds of different die configurations, ranging from a single cell die (2.5mm x 2.5mm) up to an array die that is 10 cells by 10 cells (25.68mm x 25.68mm) or even larger, to obtain a size commensurate with the IC being simulated.
How it works
Metal film resistor heat sources were chosen for their better uniformity and matching across the wafer compared to polysilicon resistors. Additionally, their relatively stable temperature coefficients of ±20ppm/°C results in constant power dissipation over the course of the thermal measurement.
The heat sources are laid out to occupy 86% of the die area, thus conforming to the JESD51-4 standard. Each heat source has a pair of contacts for power connection and a second pair of contacts for Kelvin (e.g., 4-wire) connections to measure precisely the voltage being applied to the heat source. Similarly, each of the temperature sensing diodes also have Kelvin connections, allowing one pair of connections to provide just enough forward current to operate the diode at the break of its forward current-voltage curve, while the second pair of connections can accurately measure the forward voltage. It is critical to keep the current below the point of self-heating, yet above the point that can cause problems with repeatability.
* See Figure 2a and 2b.
Creating and configuring arrays of TTCs
There are two basic concepts in creating and configuring TTCs; uniform heating and distributed heating. Uniform heating implies that the heat source is consistent across the surface of the die, eliminating any thermal gradients across the silicon surface. To achieve this, the resistances in each TTC must be dissipate the same heat and therefore must be passing the same heating current. By configuring the TTCs in the correct series, parallel or series-parallel combination, uniform heating is achieved.
For example, Figure 3 (below) shows how the two heating elements in a TTC can be configured either in parallel (for a heater resistance of 3.8ohm) or in series (for a heater resistance of 15.2ohm).
***See Figure 3
Most chip designers strive to achieve an end product whose silicon die aspect ratio is 1:1. Occasionally this isn’t possible due to I/O requirements (bonding pad locations). When an asymmetrical TTC array is needed, consideration should be given to the aspect orientation of the array. For example, thermal simulation of a die that is 13mm x 8mm can be achieved by using a TTC array that is 5×3 cells or 3×5 cells.
Both contain the same number of cells and, therefore can dissipate the same amount of power and both offer a center diode for temperature sensing. For uniform heating, both operate the same and the only difference would be the voltage and current needed to generate the same amount of power dissipation. For example, see figure 4.
*See Figure 4.
The 3X5 array has 5 series strings of resistors with each string having a resistance of about 37.5 Ohms (= 5 X 7.5 Ohms). Paralleling these strings results in a total resistance of about 6.25 Ohms. For 10W of power dissipation, a voltage of 7.9V @ 1.265A would be required.
The 5X3 array, shown in figure 5, has 10 series strings of 3 resistors with each string having a resistance of about 22.5 Ohms (= 3 X 7.5 Ohms). Paralleling these strings results in a total resistance of about 2.25 Ohms. For 10W of power dissipation, a voltage of 4.74V @ 2.1A would be required.
*See Figure 5.
Either approach works but the preference is to go with the lower current alternative since it is less stressful and will require smaller trace widths on the board where the packaged chip is mounted.
Distributed heating is actually more representative of what one might expect to see in a large ASIC or ASSP. Certain parts of the circuit that are designed for higher speed or must manage greater power are expected to dissipate more heat. Chip designers will want to know how hot these hot spots actually get and how the heat might affect circuitry on another area of the chip that might have some sensitivity to heat, such as a precision voltage reference.
TTCs are designed to accommodate either wire-bond or bumped wafer flip
chip packaging. In the wirebond configuration, the pads surrounding each
TTC are connected to their adjacent neighbor with metal. Only when the die is sawn into its desired configuration (2×2, 5×5, 7×9, etc.) is the connection severed. Conventional wire bonding techniques pretty much limit package pinout access to only those pads around the periphery of the array. Due to the way the masking is done on the wafers, the maximum chip size of wire bond chip version, is a 40X40 array, (1,600 TTCs occupying a total of 10,000mm2 ~100mm X ~100mm).
When an application calls for a more localized heating, for power mapping purposes, the flip chip design is ideal. With no internal interconnects between the TTC in the array, all bonding pads are accessible. For example, for an 8 x 8 TTC array, heat can be generated at selected cells.
***See Figure 6
Temperature sensing diodes in these and all other cells can then be used to measure heat transfer across the die. Unit Cell specifications for each TTC are important to understanding the overall expected performance of the array being used to simulate the new IC under development. See figure 7.
*See Figure 7.
In addition to single chip packages, TTCs can also be obtained in custom stacked die configurations (see figure 8) as well as multichip (horizontal layout) packages and package on package components. Custom packaging services are also available for those requirements that cannot be addressed by the standard packages described above.
*See Figure 8.
TEA recently introduced a new TTC Unit Cell size version that is 1mm X 1mm and contains a single heating resistor and a single temperature sensing diode. The smaller Unit Cell allows for greater power mapping capability. Both TTC Unit Cell sizes are available in 150mm (6”) diameter wafer form as well as sawn array chips.
Using re-distribution metal
An RDL (Re-Distribution Layer) is used to redistribute the electrical contact pads – either wire bond or bump – into a configuration other than that originally designed on the chip. Some reasons for this are:
• Mounting a chip onto BGA package substrate originally designed for a different chip pad configuration;
• Wire bond chips may have a single row of wire bond pads in the center of the chip.
• Stacked chips may require all wire bond pads along one chip edge.
The process for creating an RDL on the wafer consists of creating one or more metal layers between insulation layers. The metal layers are etched to form traces that connect the existing chip contact pads to created new pads in desired locations. Depending on the trace routing complexity, there will be multiple layers of metal and insulator stacked upon one another. The new pads can be used for wire bonding connection or act as the base for adding Flip Chip bumps.
Figure 9 is a TTC-1002 2X3 array with an RDL that provides for wire bonding either along specific locations on the periphery or down the center of the chip. The RDL is a custom requirement that needs to be discussed in detail with TEA before any implementation can begin.
*See Figure 9.
How hot is hot?
Calculating power density using empirical data derived from Thermal Test Chips, IC designers and packaging engineers can model the actual performance of a product well in advance of committing a design to silicon or a package to hard tooling. Semiconductor process advancements are merging heretofore incompatible pieces of complex systems onto a single substrate. Gone are the days of isolating the power elements to their own heat sunk packages. Now they reside a few microns away from temperature sensitive structures. Something has to give. Or does it?
The use of Thermal Test Chips allows designers to precisely pinpoint the heat sources on their designs and simulate its effect on the performance of the entire system. Take the 2.54mm x 2.54mm Unit Cell discussed earlier. With its two 7.6ohm resistor heating elements, each capable of handling 1 Amp at 6 Volts, the cell can dissipate 12 Watts of power. Its area (6.45mm2) yields a power density of 186W/cm2. The newly introduced 1mm x 1mm Unit Cell with its single 10.5? resistor heating element, capable of handling up to 0.55 Amps at 5.5Volts, can dissipate 3 Watts of power. Its area (1mm2) yields a power density of 300W/cm2.
Combining Unit Cells into an array derates these figures slightly due to the additional silicon required for saw streets between the cells. For example a 10 x 10 array of the 6.54 square mm cell has a power density of 182W/cm2, while a 10 x 10 array of the 1 square mm cell has a power density of 261W/cm2. These are exceptionally high PDs and are difficult to achieve by other means.
In power mapping applications, these high PDs per unit area offer the user an opportunity to better simulate power density levels resulting from multi-point localized heating in high performance CPUs and ASIC chips. Additionally, they can better simulate high power and high frequency transistors – SiC (Silicon Carbide) and GaN (Gallium Nitride).
Although seldom discussed in public journals, the use of these Analog ASIC Thermal Test Chips play an important role in allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production.
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