Pre-silicon verification set for a time-crunching, virtualized overhaul

The pressure on chip production timelines is unprecedented.

Operators and hyperscalers are racing new offerings to market as end users show a hunger for higher and higher speeds. 400G is entering the mass market deployment phase. 800G equipment is hitting networks in search of next-gen use cases. And, of course, 5G, SD-WAN, IoT and edge cloud are standing by to deliver a dizzying lineup of new experiences.

Such heavy demand couldn’t come at a more challenging time for the silicon market. COVID has created industry-wide ripples affecting chip development, production and deployment timelines. Supply chains are on the mend, but now, stakeholders are desperate to make up for lost time. Advancements in pre-silicon verification and post-silicon validation testing are revealing a path forward.

No time for old processes

The inefficiencies in silicon development workflows have been tolerated for far too long. It’s a familiar story of wearisome, time-consuming back-and-forths between design teams and manufacturers. Cycles fraught with problem-prone processes tend to consume upwards of years and play out on a global stage.

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During pre-silicon verification, designs are typically only being tested for speed – not scale. The chips have no knowledge of the network services that will actually rely on them. So, if performance checks out, the design is shipped halfway around the world for production. Inevitably, bugs are baked into the silicon but not discovered until the faulty chip is developed or deployed. Then it’s back to square one for a redo. Millions of dollars and dozens of months of wasted time vanish in the process.

It’s no wonder so many stakeholders just skip pre-silicon verification entirely. Of course, they usually end up paying down the line as missed bugs rear their ugly heads in the post-silicon validation phase. The fallout can be extraordinary. The National Institute of Standards and Technology estimates that the cost of discovering defects after release may be up to 30 times more expensive than making these discoveries earlier in the design phase.

That’s to say nothing of the reputational damage at stake. Cautionary tales abound of chipset makers earning black eyes for their brands following discovery of an avoidable bug in a highly-adopted product. But, this doesn’t have to be. It is time to standardize on pre-silicon verification and post-silicon validation driven by an automated, emulation-based approach. Critically, the pre-silicon verification phase must take into account the needs of operators that will actually deploy the networking equipment – be it a router, switch or server.

Put simply, pre-silicon verification needs to start looking more like key elements of post-silicon validation. Virtualization and software are set to play a starring role.

Testing chips at the networking layer with a virtualized approach

As noted earlier, the physical Electronic Design Automation (EDA) emulation systems that have been used for pre-silicon verification weren’t built to test scale. These imposing, garage-sized installations generate traffic into a couple dozen physical ports based on various test requirements. Tedious, manual testing processes then play out for each port and interface.

Now, the chip industry is virtualizing making way for EDA transformation with more flexible software, pressure to speed up the design process, and importantly, they need to able to leverage traffic emulation capabilities already being used in network testing. Crucially, this means pre-silicon verification can test not just for Ethernet speed, but scale. In other words, chips leave the design phase having already been tested under the very means by which they’ll be deployed.

Unconstrained by a certain number of pre-purchased test ports, virtualized testing can support the scale and automated workflows needed to quickly test thousands of ports and easily modify the functional building blocks being tested. This could include emulation of any protocol or traffic situation at just a moment’s notice.

Initially, complete silicon emulation at the Layer 1 level is helping pre-silicon verification take a giant step forward. Eventually, it will be possible to conduct a range of tests in parallel. Imagine Layer 1, 2 and 3 protocols being verified at the same time Layer 4 to Layer 7 verification takes place. Importantly, engineers need not be expert in these specific areas. Growing libraries of test scenarios will be deployable in an automated fashion to keep teams moving swiftly.

What does this mean for real-world timelines? In our early work with chipmakers and EDA companies, we have already seen automated workflows shrink the time it took to set up testing environments from 50 hours to just ten minutes – a 300x acceleration. That’s not all. We’ve seen chipset vendors exponentially increase the number of test cases conducted from just seven per day to as many as ten per hour. They’ve also been able to increase test hours per week from 40 to nearly 170. They have slashed regression cycles from weeks to just days.

Now we’re talking.

Automation for the win

Incorporating intelligent, programmable, easily updatable software into the pre-silicon stage is a gamechanger. It is being proven to reduce chipset development cycles and introduce flexibility that creates the foundation for testing at real scale. This means bigger, more complex chips can be designed faster and at higher quality.

Yes, they may still have to get shipped around the world for production. But when they come back, they are ready for primetime. They are proven to meet high industry standards. Most significantly, they are ready to deliver on some of the most complex, time-critical demands ever faced.

The post-COVID world will be defined by speed. So much of the technology we have anticipated for so many years stands at a critical inflection point. The behind-the-scenes hero emerging to make it possible will be simplified, virtualized testbeds powered by automation. To be sure, pre-silicon verification advancements won’t happen in a vacuum. While chipset makers recognize the value of investing more heavily in early test phases, an entire ecosystem will have to come together in pursuit of a better approach.

It will be worth the effort.

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Malathi Malla is head of go-to-market strategy & operations at Spirent Communications, a global provider of automated testing and assurance solutions for networks, security and positioning.