How the SEMI industry will succeed in another $100B growth
Paul Marchal, director of technical marketing at imec, discusses three main technologies that will enable further growth for the semiconductor industry. Marchal was a guest speaker during the imec technology forum held recently at the Semicon West show in San Francisco.
Industry analysts expect semiconductor industry to expand within the next five years to $400B, driven by three large application domains: smart phones and tablets, the associated infrastructure needed to support wireless data and finally the internet of things that emerges, with applications in healthcare, logistics and consumer goods.
The above growth is fueled by further advances in logic scaling, progress in material sciences enabling new memory concepts such as STT MRAM; advanced packaging solutions such as silicon interposers and 3D integration; and other More Than Moore (MtM) technologies enabled by advanced packaging. All these technologies together provide a platform for reducing power and form-factor; and for increasing the system performance.
Logic scaling: complex and costly
Gordon Moore said that no exponential is forever, but we can delay forever. Today, there is no doubt that we can further improve transistor performance and reduce the power consumption down to the 5nm node. There are many options to boost performance and increase density. We are working on new concepts in litho such as EUV, multi-patterning and directed self-assembly; in device engineering such as non-silicon channels (III-V/Ge or SiGe); in BEOL such as alternate barrier technologies and ELK materials. However, the truth is that every disruption increases complexity. Also, it may require new tool investments and thus ultimately increases NRE & capex. More than ever, the semiconductor industry needs to collaborate to share R&D for identifying a worthwhile scaling path.
Also for the fabless companies, this evolution has consequences. First, they need to steer the technology definition (‘technology pathfinding phase’), the technology choices need to be driven by architecture needs. The most cost-effective options must be taken, making sense from a design point of view. Fabless companies should in an early stage understand how the technology may impact their architecture, giving them the time to adapt. To address above challenges, we are providing fabless companies with device models and cost estimates and we give them an idea of the maturity of the different options.
Secondly, we help fabless companies during the design for manufacturing phase to understand how they need to fine-tune the designs for yield based on our fundamental understanding of the process. For example, we are using litho simulations to indicate hotspots in the designs. Finally, we help fabless companies to set up the infrastructure to monitor yield and possible causes of yield loss during ramp.
Advanced packaging: mature technology but yield and cost are an issue
Next to logic scaling, advanced packaging is an enabling technology for semiconductor growth, supporting many new applications: logic-on-logic, multi-node integration, DRAM stacking, DRAM/logic stacking, radio/analog and logic stacking, optical and logic stacking etc. The 3D integration technology is relatively mature. The biggest barrier for its adoption today is the industry’s limited experience ramping its yield. For instance, it’s hard to control co-planarity of microbumps during stacking, necessary for achieving good yield.
Provided the small geometries, co-planarity must be below 1.5µm, which is a big challenge. Besides, the combination of many different materials inside a stack with very soft BEOL layers may easily become a reliability headache. We are supporting fabless companies in their 2.5/3D integration efforts by providing them with designs optimized for manufacturing yield and help them select the right materials and assembly approach.
Silicon photonics: an important MtM technology
3D is an outstanding technology that enables an entire new field of MtM integration. A promising example of such a technology is silicon photonics. This technology can provide an answer in the field of wireless communications. It is well known that the bandwidth of the wireless network needs to increase by a factor of 1000 in the coming five years. This means that the bandwidth of the chips’ input/output interface has to increase with a factor 1000 or the area/Gbs has to be reduced. Classical electrical solutions don’t scale in this way because of physical limits. Optical IO may be a better way to go.
Today, work is done on integrating these optical IO in a 3D fashion. 3D integration provides massive bandwidth between the optical subsystem and the logic die at low energy consumption. Heterogeneous (3D) integration and in particular silicon photonics are not always available as off-the-shelf options in a foundry. Because of this, we develop prototypes and low volumes to companies, based on our expertise through our R&D work and based on our state-of-the-art infrastructure.
With this, we have provided you a glimpse of the technology innovations and its challenges that will bring the semiconductor industry a $100B growth in the next five years. That’s something to look forward to.
***For more information about logic scaling and how design houses should be involved from the very beginning; the challenges in 3D packaging; and the huge promise of optical I/O; visit the website: