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Synopsys’ ASIP Designer Virtual Seminar 2020

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December 03, 2020


The slowing down of Moore’s law and Dennard scaling triggered an increased awareness for domain-specific processors, also referred to as application-specific processors (ASIPs). These processors implement a specialized instruction set architecture (ISA) tailored to the application, often starting from a baseline ISA such as RISC-V.
December 3, 2020
9:00 a.m.–11:30 a.m. PT

Join us at Synopsys’ ASIP Designer Virtual Seminar 2020 to learn why ASIPs are getting so much attention these days, and why Synopsys’ ASIP Designer is the industry’s leading tool to design, implement, program and verify such specialized processors. The following topics will be covered:

  • An Introduction to ASIP Designer
  • RISC-V ISA example models, and the concept of Simple Datapath eXtensions (SDX)
  • Case study: Designing a programmable AI accelerator for MobileNet V3

If you are a design engineer, algorithm developer, software engineer, system architect, or design manager focusing on advanced SoCs requiring application-specific optimizations,



Visit event's website
https://www.synopsys.com/designware-ip/processor-solutions/asips-tools/asip_seminar.html?mkt_tok=eyJpIjoiWldJek1ERXpNV1UwWkRRMCIsInQiOiIxK0VDZHkrTXJ3ektnR2M2SnIwcm9rVVRoRjB5dTFUWWR3YWswQ1d3UG1LY3ZJTkdxc2NhWW5cL2ROXC9CdVhiOU1tdEZvZ1BxbWxuR3VVOTFjWlZJQ2JqaVYzekJQY2JlZWowVmYzcDM0aDJuR2lKdUVPSGhha09MSFR2WkduQ3I3In0%3D




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