MIPI D-PHY v3.0 doubles data rate of physical layer interface
EP&T MagazineElectronics Regulations & Standards MIPI specifications standars
C-PHY extends power efficiency, enhanced with 64-bit PHY Protocol Interface
The MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today announced a major update to its MIPI D-PHYspecification for connecting megapixel cameras and high-resolution displays to application processors. Version 3.0 doubles the data rate of D-PHY’s standard channel to 9 Gigabits per second (Gbps), while extending the power efficiency of the specification for smartphone, Internet of Things (IoT) and automotive camera and display applications.
As the first MIPI PHY specification introduced more than 15 years ago, MIPI D-PHY has been broadly implemented as the physical-layer interface for cameras and displays in smartphones because of its cost-effective flexibility, high speed and low power. Due to these attributes, the specification has also been applied to a wide array of other use cases such as drones, very large tablets, surveillance cameras and industrial robots, as well as automotive applications, including camera sensing systems, collision avoidance radars, in-car infotainment and dashboard displays, with the support of proprietary bridging solutions.
D-PHY v3.0 doubles the specification’s speed to 9 Gbps for the standard channel (and 11 Gbps for its short channel), enabling support for the latest ultra-high-definition displays and beyond. In tandem with the boost in data rate, D-PHY v3.0 introduces a Continuous-Time Linear Equalizer (CTLE) on the receiver side of a connection to maintain the interface’s superior power efficiency. D-PHY v3.0 is fully compatible with previous versions of the MIPI specification.
“Pixel rates in camera and display applications are constantly increasing, and v3.0 of D-PHY provides the leap in data rate necessary to support next-generation image sensors while extending the specification’s low-power attribute,” said Joel Huloux, chairman of MIPI Alliance. “MIPI continues to innovate its PHY interfaces to enable advancements in camera and display applications and emerging market dynamics.”
In conjunction with the release of D-PHY v3.0, MIPI Alliance also announces version 2.1 of MIPI C-PHY, which provides high throughput and superior power efficiency to connect displays and cameras to application processors. The specification supports symbol rates up to 6 Gigasymbols per second (Gsps), equivalent to 13.7 Gbps, over the standard channel and up to 8 Gsps over the short channel. A new 64-bit PHY Protocol Interface (PPI) in v2.1 provides a wider bus between C-PHY and a chip’s core logic for better support of higher-performance applications. The new version of the interface is fully compatible with previous versions of C-PHY.
In addition to the added features, the new version of the C-PHY specification replaces objectionable terms with ones that more accurately reflect the functions of technical devices.