New MIPI debug and trace solution available
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New specification serves mobile, IoT and automotive designs
The MIPI Alliance an international organization that develops interface specifications for mobile and mobile-influenced industries, announced the public availability of MIPI Debug for I3C v1.0, a flexible and scalable debug and test specification for systems that enable 5G, the Internet of Things (IoT), automotive and other applications.
This new specification, built on the MIPI I3C v1.1 (and MIPI I3C Basic v1.0) utility and control bus, allows system designers to efficiently and dynamically debug and test application processors, power management integrated circuits, modems and other power-managed components across a system of any size via the low-bandwidth MIPI I3C interface, which requires a minimal set of pins.
“MIPI Debug for I3C overcomes the limitations of current low-bandwidth solutions available in the market and delivers a simple interface scalable and flexible enough for use in scenarios throughout a product’s lifecycle,” said Joel Huloux, chairman of MIPI Alliance. “In leveraging and expanding the applications of the MIPI I3C interface, MIPI continues to fuel the growth of a rich development ecosystem around standardized debug and trace, translating into greater interoperability and capabilities, and cost advantages for OEMs, silicon providers and system developers.”
Delivers multi-component connectivity
Legacy low-bandwidth interfaces such as JTAG/cJTAG, I2C and UART that are structured statically impose limitations on the accessibility of debug components and devices—for example, when they’re in low-power mode. MIPI Debug for I3C overcomes these restrictions by building on key MIPI I3C v1.1 features. MIPI Debug for I3C delivers multi-component connectivity across either dedicated debug or shared bus topologies, requires only two wires, supports multiple entry points, and maintains a network even as components power down and off a network and then rejoin after powering back up.
The interface transports debug controls and data between a debug and test system (DTS) and a target system (TS). The TS exposes multiple debug interfaces/ports from a single physical connection, and the DTS then sends broadcast or directed action requests (halt, reset, etc.). Event indications can be sent via in-band interrupts (IBIs), and communication takes place over defined, byte-oriented streaming interface ports that can support different protocols. No special I3C controller hardware is required.
Existing common command codes
Leveraging MIPI I3C’s multi-drop, two-wire architecture, as well as its existing common command codes (CCCs) and device “hot-join” ability, Debug for I3C supports key specialized extensions for debug and trace:
- Defining debug-specific CCCs for configuration, function selection and action/event triggers and interrupts
- Assigning specific Mandatory Data Byte (MDB) values to indicate debug IBIs
- Standardizing data-exchange mechanisms for predefined port-based communication
“Low-bandwidth interfaces for debug and trace are increasingly essential with the proliferation of smaller and more power-constrained systems, yet the requirements of these new use cases have exposed crucial shortcomings in the solutions currently available,” said Enrico Carrieri, MIPI Debug Working Group chair. “MIPI Debug for I3C uniquely handles the network topology in a dynamic fashion, so it’s perfectly suited for the use cases and challenges being faced today in design and development.”