Cadence Design Systems Inc. has announced its SPB 16.2 release, which focuses on addressing current and emerging chip package design challenges. This latest release delivers advanced IC package/system-in-package (SiP) miniaturization, design cycle reduction and DFM-driven design, along with a power integrity modeling solution. These capabilities are designed to boost productivity of digital, analogue, RF and mixed-signal IC package designers involved in single and multi-die packages/SiPs. Design teams can expect improvements in the reduction in overall package size through the introduction of rules and constraint-driven automation capabilities that address the design methodology of high-density interconnect (HDI) substrate manufacturing that is a key enabler for miniaturization and increased functional density. The new power integrity technology allows designers to efficiently address the power-delivery design goals of sufficiency, efficiency and stability.