Power Reduction in Digital Circuits

DatesFebruary 26 2013
CityMarkham, Ontario, Canada
Location1 Commerce Valley Parkway
Contact NameJanet Rawding
Local Phone905-602-8345
Emailjrawding@itac.ca
Websitehttp://bit.ly/XmvNHB
SponsorsHosted by Advanced Micro Devices (AMD)
TopicsSpeakers - Digital Systems:

Paul Lamers, Senior Staff Applications Consultant at Synopsys, Ottawa, ON
Ken Wagner, Distinguished Engineer at PMC-Sierra, Vancouver, BC (and Adjunct Professor ECE, McGill)
Main BodyIn spite of reduction in supply voltage and improved leakage control, power consumption has become a key performance specification/target in many electronic products – not just portable electronics. Reducing power consumption requires a broad multi-dimensional approach: system power management; energy efficient regulation; architectural optimization; on-die power management; BIG-Little processors; low-power implementation techniques (clock and power gating, multi-Vt, multi-channel libraries, leakage and dynamic power optimization), sleep modes, etc.
FeesCost (Please note that the registration fee covers the cost of dinner)
ITAC Members - $45.00 + HST
Non-members - $65.00 + HST