Flower Technology Inc., London ON-based start-up focused on the supply of ASIC mining solutions for scrypt-based cryptocurrencies, has partnered with EnSilica, a leading UK design house and provider of the eSi-RISC family of soft processor cores and associated encryption, communications and peripherals IP, for the development of the company’s rack-mounted, low power, high performance ASIC scrypt miners.
Flower Technology’s first product, called Orchid, will provide a performance of 20Mh/s (megahashes per second) with a power consumption of just 4W/Mh (watts per megahash. The Orchid scrypt miner will be priced at US$1,900 with delivery expected to commence in Q3/Q4 2014.
“Drawing extensively on EnSilica’s design expertise and cryptographic knowledge, Orchid will set a new standard in hashing speed, energy efficiency and price/performance for ASIC scrypt miners,” says Brock Huxtable, CEO of Flower Technology. “EnSilica’s algorithm team has already completed work on a novel, clean-sheet architecture – dubbed a Massive Array of Scrypt Threads (MAST) – with parameterized RTL ready to be taken to the physical implementation phase of the design.”
The MAST architecture comprises a highly parallel and dedicated array of scrypt threads which enables the hardware to completely reconfigure itself every clock cycle according to the threads that are in progress. In this way every computational hardware element is kept busy doing useful work on every clock cycle enabling the architecture can have a deep pipeline without loss of performance. With over a 1,000 threads in partial computation at any one time and with a new hash starting every 64 clock cycles, a single chip achieves a hashing performance of 10M/hs at a worst case corner clock speed of 640MHz.
Dr David Wheeler, EnSilica’s technical director and a recognized authority on hardware-based cryptography, communications and DSPs, heads the EnSilica development team. director of SoC engineering, Andy Maund, who has taped out over 30 GPU and media processor design at leading-edge technology nodes, leads the ASIC physical implementation and software lead, James Wilkins, takes responsibility for the embedded software design, mining software ports and user interface.
EnSilica’s physical design team is currently engaged in the next phases of the IC development including a detailed analysis of the foundry, technology and physical IP required to meet the demands of the application. Exploration of the power, performance and area trade-offs involved with different technologies, cell libraries and memory compilers is also underway. This work will take the design through full place-and-route, giving power and performance figures that will correlate closely with the actual silicon.
“It is imperative to make key technology and IP decisions before pushing on with the detailed design,” said David Wheeler, EnSilica’s technical director. “A systematic approach reduces will reduce overall time-to-market and deliver a solution optimized for both low power and high performance. The architecture we have developed coupled with the use of a leading-edge submicron process will achieve the lowest power consumption per megahash of any ASIC in development.”