This flow is based on the Common Power Format (CPF) for Cadence technology. “It enables Andes to provide its customers a scalable and configurable low-power management framework that blends hardware and software solutions,” said Andes. “Teaming with Cadence, we were able to shorten the development cycles for our SoC platform IP products implementing the AndesCoolâ„¢ low-power management feature, built on top of the CPF design and verification flows. By integrating CPF into our AndesCool framework, we are now getting ready to provide our customers a robust and flexible reference solution to help them hit their low-power targets efficiently and consistently,” said James Lai, associate vice president of Andes.
The Cadence approach is a design based on a single, consistent notion of power intent. It provides an “integrated power-intent specification throughout the entire ASIC design flow that has helped shorten development cycle.”
The specific technologies adopted are: Encounter RTL Complier, Encounter Conformal Lower Power and Incisive Enterprise Simulator.