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Implementation Strategies for USB Circuit Protection

Figure 1. Circuit protection and power switching requirements for USB.{toggle author}The USB specification requires current limiting and/or power switching for USB power management, and references resettable polymeric positive temperature coefficient (PPTC) devices and solid-state switches as acceptable methods for overcurrent protection. Resettable current limiting in a fault condition helps prevent circuit damage and associated system failure, and helps the system meet UL safety standards.


Like fuses, PPTC devices help protect circuitry from overcurrent damage. Unlike fuses, however, they reset when the circuit is de-energized and the fault is removed. Protected power switch devices integrate resettable current limiting functionality with power switching, and are most commonly used in bus-powered hubs, in dual-mode hubs, and in low-power hosts. They function as inrush current limiting devices, and combine low resistance with extremely fast current limiting. They are a practical, cost-effective solution for power-constrained hosts where a fast current limiting response further reduces system voltage droop in a fault condition, and where power switching can be used to improve energy conservation.

Industry Specification Requirements
The USB specification states that current limiting, power switching, or both may be required in a USB product, as shown in Figure 1. Where current limiting is required, the UL 60950 specifications must be met. This means that in the event of a short circuit or other fault condition, current output must be limited to below 5A within 60 seconds. The USB specification also defines acceptable voltage output levels and limits total voltage drop in the system.

Protected Power Switch Technology
Protected power switch devices are silicon series elements used in the USB power bus to control the flow of power to ports and to protect circuitry and devices from damage caused by overcurrent. Like the PPTC device, the protected power switch trips in an overcurrent condition, but it does so in a two-phased approach. The device ‘trips’ in microseconds, limiting current to a predefined range that is higher than nominal operating current, and then flags the controller that a fault condition has occurred. The controller can then shut down the port by toggling the enable pin on the power switch. If the controller does not respond, the power switch cycles the port on and off to prevent thermal damage.

Parameters
The critical device parameters in USB applications include switch resistance, continuous output current, time-to-trip, current limit set point, fault flag delay, current limit release point, and tripped current draw.

Switch Resistance
Switch resistance can affect both system power draw and the end-user experience, and is measured through the device when it is not in current limiting mode. High switch resistance can result in excessive voltage drop through the device, which can result in USB non-compliance and improper device functionality. Silicon switch resistance can be a function of supply voltage, and the best device will minimize resistance and voltage drop at lower bus voltages in order to maintain USB output voltage compliance.

Continuous Output
Continuous output current is the current level at which the device will not trip. For systems with low wattage power supplies this should be set as low as possible while still supporting the USB specification. This will help minimize voltage drop in short circuit conditions.

Time-to-Trip
Time-to-trip defines the speed at which a protected power switch device activates its current limiting circuitry. The extremely fast time-to-trip of the silicon device makes it the preferred choice for power-constrained applications. Unlike the PPTC device, however, post trip current levels can remain fairly high, and are defined by the current limit set point.

Current Limit Set Point
The current limit set point is the level at which a silicon device will limit current once it has tripped. Its value can vary depending on the severity of the fault condition, and is typically defined as a function of the fault condition’s resistance. For low-power applications, the current limit should be specified as low as possible.

Fault Flag Delay
Integrating a fault flag delay with the silicon device helps prevent ‘nuisance tripping’ and improves the end-user experience. The fault flag is a logic level output that alerts the USB controller when there is a problem with a specific USB port. During USB hot plug events, many USB functions are highly capacitive and can draw significant current, exceeding specification limits. This causes the device to trigger a short-lived current limiting condition that, if signaled to the controller, will cause nuisance tripping. A 9-millisecond fault flag delay prevents these short-lived events from triggering the fault flag.

Current Limiting Release Point
The current limiting release point is a critical parameter for the end-user experience. This is the current level at which the silicon device will disengage its current limiting function. This is an important design consideration because once current limiting is active the device resistance is dramatically increased and may prevent proper functioning of an attached USB device. If set too low, a device that enters current limiting mode during hot-plug may remain tripped when initial inrush currents subside, preventing proper USB function operation. By setting current limiting release points above 500 mA, the protected power switch will cease to limit current once the USB device returns to normal operating current levels.

Tripped Current Draw
Initial power dissipated at the port after a trip event is a function of the silicon device’s limit current. If the device can be turned off during a fault condition, port current draw and power draw are negligible. If, however, control circuitry is not implemented (e.g. the enable pin is tied high in a high enable device, or power switching is not integrated into the device) most silicon devices will continue to limit current until they reach an internal temperature threshold. When the temperature threshold is reached they will begin to thermally cycle the port on and off. Average port current draw under these conditions will be a function of the thermal duty cycle, and the current limit. For low-power applications using silicon devices, it is important to implement proper on/off control circuitry to prevent high, ‘tripped’ power dissipation.
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Summary
Protected power switches can integrate numerous detection and protection functions in USB power management applications, resulting in improved performance and reduced component count. Specifying the appropriate device requires consideration of several critical device parameters to provide system reliability, and meet end-user expectations.

Adrian Mikolajczak is multimedia market manager at Tyco Electronics Power Components/Raychem Circuit Protection Group.


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